Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts

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International Symposium on Quality Electronic Design (ISQED '01)

San Jose, California

March 26-March 28

ISBN: 0-7695-1025-6

	ASCII Text	x
	J.W. McPherson, "Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts," Quality Electronic Design, International Symposium on, pp. 123, International Symposium on Quality Electronic Design (ISQED '01), 2001.

	BibTex	x
	@article{ 10.1109/ISQED.2001.915216, author = {J.W. McPherson}, title = {Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1025-6}, pages = {123}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915216}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts SN - 0-7695-1025-6 SP EP A1 - J.W. McPherson, PY - 2001 VL - 0 JA - Quality Electronic Design, International Symposium on ER -

J.W. McPherson, Texas Instruments, Inc.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915216

Scaling, for enhanced performance and cost reduction reasons, has pushed existing CMOS materials much closer to their intrinsic reliability limits. Future robust designs will require a strong team effort whereby the design engineer must clearly understand the process variability and its impact on reliability. This strong team effort, between design and process, will become critically important as the industry is seeking to replace the very materials that has made the industry so successful: Si substrates, SiO2 gate-dielectric, Al-based metallization and SiO2 interconnect-dielectrics.

Citation:

J.W. McPherson, "Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts," isqed, pp.123, International Symposium on Quality Electronic Design (ISQED '01), 2001

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