This paper reviews recent progress in making circuit-level CAD tools for the design of digital integrated circuits SOI-aware, specifically transistor-level static timing and static noise analysis tools. This involves abstracting the SOI device physics of the floating body, allowing estimates of the body voltage variation under various switching activity assumptions. These body voltage estimates are then applied as "initial conditions" in the constituent simulations of the static analyses. Results are presented for a prototype static timing analysis tool and a commercial static noise analysis tool.