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International Symposium on Quality Electronic Design (ISQED '01)
I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os
San Jose, California
March 26-March 28
ISBN: 0-7695-1025-6
ASCII Text
x 
 
Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous, "I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os," Quality Electronic Design, International Symposium on, pp. 71, International Symposium on Quality Electronic Design (ISQED '01), 2001.
 
 
BibTex
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@article{ 10.1109/ISQED.2001.915208,
author = {Gulsun Yasar and Charles Chiu and Robert A. Proctor and James P. Libous},
title = {I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2001},
isbn = {0-7695-1025-6},
pages = {71},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915208},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os
SN - 0-7695-1025-6
SP
EP
A1 - Gulsun Yasar,
A1 - Charles Chiu,
A1 - Robert A. Proctor,
A1 - James P. Libous,
PY - 2001
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Gulsun Yasar, IBM Microelectronics Division
Charles Chiu, IBM Microelectronics Division
Robert A. Proctor, IBM Microelectronics Division
James P. Libous, IBM Microelectronics Division
Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related rules used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.
Citation:
Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous, "I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os," isqed, pp.71, International Symposium on Quality Electronic Design (ISQED '01), 2001
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