A "Design for Verification" Methodology

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	Similar Articles Articles by F. Sforza Articles by L. Battù Articles by M. Brunelli Articles by A. Castelnuovo Articles by M. Magnaghi

International Symposium on Quality Electronic Design (ISQED '01)

San Jose, California

March 26-March 28

ISBN: 0-7695-1025-6

	ASCII Text	x
	F. Sforza, L. Battù, M. Brunelli, A. Castelnuovo, M. Magnaghi, "A "Design for Verification" Methodology," Quality Electronic Design, International Symposium on, pp. 50, International Symposium on Quality Electronic Design (ISQED '01), 2001.

	BibTex	x
	@article{ 10.1109/ISQED.2001.915205, author = {F. Sforza and L. Battù and M. Brunelli and A. Castelnuovo and M. Magnaghi}, title = {A "Design for Verification" Methodology}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1025-6}, pages = {50}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915205}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A "Design for Verification" Methodology SN - 0-7695-1025-6 SP EP A1 - F. Sforza, A1 - L. Battù, A1 - M. Brunelli, A1 - A. Castelnuovo, A1 - M. Magnaghi, PY - 2001 KW - functional verification KW - testbenches KW - simulation KW - emulation KW - prototyping KW - IP re-use. VL - 0 JA - Quality Electronic Design, International Symposium on ER -

F. Sforza, STMicroelectronics

L. Battù, STMicroelectronics

M. Brunelli, STMicroelectronics

A. Castelnuovo, STMicroelectronics

M. Magnaghi, STMicroelectronics

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915205

New tools are getting available on the market that help alleviating the problem and improve the quality of functional verification of today's complex systems. A methodology that makes use of such tools is described and compared to the traditional approach followed in the context of a specific project. The scope is limited to functional verification but spans from block- to system-level.

Index Terms:

functional verification, testbenches, simulation, emulation, prototyping, IP re-use.

Citation:

F. Sforza, L. Battù, M. Brunelli, A. Castelnuovo, M. Magnaghi, "A "Design for Verification" Methodology," isqed, pp.50, International Symposium on Quality Electronic Design (ISQED '01), 2001

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