Although digital circuits are inherently immune to most sources of noise, the scaling of supply voltages and MOSFET threshold voltages has resulted in lowered noise margins. Most CMOS circuits continue to have considerable immunity to power supply and substrate noise even with the aggressive scaling used today. However, the effect of capacitive coupling noise has become a major concern for designers of deep sub-micron circuits. Compounding these problems is the fact that there are very few, if any, reliable tools for detecting coupling noise on large and complex digital circuits.This paper discusses the coupling noise analysis method used during the development of the UltraSPARC-III microprocessor. A good noise analysis strategy should not only pick out the noise violations in a design but also be robust enough to run a sensitivity analysis, with the aim of recommending solutions to the problems found. The model presented places emphasis on its scalability to large datasets, such as the design database of modern high performance microprocessors, comprising of several million transistors. A hierarchical approach to achieve this is proposed and the capacity achieved is illustrated with results on real circuits.