Degradation of lithographic pattern fidelity is a major cause of yield loss in VLSI manufacturing. A general methodology for full-chip analysis and improvement of yield loss due to lithographic effects is proposed. The approach is based on: a) extraction of pattern fidelity statistics using a full-chip layout engine, b) full-chip Optical Proximity Correction (OPC) to improve pattern reproduction, and c) estimation of yield losses due to line variability, using transistor sensitivity to pattern registration obtained from physical transistor modeling. As a result, yield estimates related to either pattern reproduction fidelity or transistor parametric data variations (such as leakage or drive current) are generated. The method is efficient and well suited for application to modern VLSI designs of memory or logic devices.