Not so long ago, the technology independent design style was advertised as the way to go, at least for ASICs. Seamless mapping of RTL code onto pre-characterized IP libraries and automatic P&R seemed to provide a smooth path from HDL to mask layout. Unfortunately, this approach does not appear to be feasible in the deep submicron (DSM) era, especially for high performance IC's.To achieve top performance while maintaining satisfactory manufacturing yields, the technology capabilities, including quasi-transmission line effects in interconnections, must be extracted and abstracted to be used up-front in the design synthesis. The design-manufacturing interface must be changed in order to account for these DSM effects, while still being able to handle the increasing complexity of designs.This panel will address the requirements imposed on the design - manufacturing interface for the DSM technologies by gathering experts from the different segments of the semiconductor industry, to address design needs versus available solutions and potential show-stoppers in designing high complexity chips for leading edge technologies.