This paper describes an algorithm and automated physical design methodology for noise sensitive dynamic circuits using a systematic shielding strategy to reduce capacitive coupling. As process technology scales, the wire width and spacing become smaller, while wire thickness is proportionately higher. This results in increasing capacitive coupling between neighboring wires, which increases wire propagation delay and crosstalk of neighboring the wires. More importantly, coupled noise or crosstalk can affect the functionality of noise sensitive receivers. Thus, for noise sensitive datapath and control blocks, shielding signals from each other has become a necessity for implementing reliable circuits.The methodology and tool described in this paper were used to reduce the design time of domino logic control blocks in the UltraSparcIII(tm) microprocessor. The two blocks reported here had delays half that of their static CMOS counterparts, the same area as the static design, cupucitive coupling noise of less than 5% of VDD, and were designed in record time using the tools.