Metal electromigration affects the functionality and lifetime of integrated circuits. This problem has so far been addressed by imposing simple design rules and current density limits during the design and validation of Ics, but a barrier has been reached in UDSM. State-of-the-art, high-speed circuit designs require current densities in signal nets close to the material limits to meet timing budgets. The validation of electromigration reliability becomes imperative. This paper introduces analysis techniques specifically for signal net electromigration validation at the full-chip level. Results of this analysis provide feedback to the designer to permit engineering decisions between opposing design constraints with consideration to electromigration reliability.