This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural layout approach is shown to be best suited for this kind of methodologies. Once captured, the procedural description can be used several times to calculate both rapidly and accurately all parasitics that appear during physical realizations without layout generation. Efficient algorithms are developed to take into account analog layout constraints such as matching, parasitic control, shape and reliability considerations. This allows accounting for these effects early in the design, which guarantees the fulfillment of the required performance specifications, %in the presence of layout parasitics, permits to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.