This high-level panel will look at important ? but often overlooked ? global, social and economic implications of design quality. It will probe the costs, to both end users and manufacturers, of poor quality. Only by accounting for these costs can manufacturers gauge the importance of proper verification and design techniques.The goal of this panel is to identify some of the quality-related problems that could plausibly occur, discuss their consequences, and propose some solutions for improving the quality and reliability of electronic designs. This panel will also probe the question of who takes responsibility when silicon fails. Assuming that the wafer fab process is yielding correctly, and the chip is not working due to a design quality problem, then who pays what price? How is responsibility shared among systems companies, IP providers, and semiconductor manufacturers?