First International Symposium on Quality of Electronic Design
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
San Jose, California
March 20-March 22
ISBN: 0-7695-0525-2
The use of low threshold devices in low voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of IDDQ testing for such low voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit IDDQ testing. In this paper we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of IDDQ testing. Results on a large number of benchmarks indicate that dual threshold and vector control techniques are very effective in improving fault coverage for IDDQ testing.
Citation:
Zhanping Chen, Liqiong Wei, Kaushik Roy, "On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques," isqed, pp.181, First International Symposium on Quality of Electronic Design, 2000