Several approaches that address early power estimation in digital design have been published in the last years. Most of them are based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist. In this paper we present a summary of RTPow, a proprietary tool dealing with the RT-level power estimation, relying on a top-down estimation engine that does not perform any type of on-the-fly logic synthesis when analyzing the HDL description. In addition, a set of power macromodeling capabilities have been developed as well, to enable an effective power budgeting and automatic bottom-up power characterization methodology.