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First International Symposium on Quality of Electronic Design
Transistor Modeling for the VDSM Era
San Jose, California
March 20-March 22
ISBN: 0-7695-0525-2
Michael S. Shur, Rensselaer Polytechnic Institute
Tor A. Fjeldly, Norwegian University of Science and Technology
Trond Ytterdal, Nordic VLSI
We review field effect transistor modeling with emphasis on device parameter extraction for testing. We consider the physics-based universal charge control model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion regimes in MOSFETs using a relatively small set of parameters, most of which are related to the device structure or fabrication process. This small parameter set makes the task of parameter extraction easier. The model accounts for velocity saturation, finite output conductance in saturation, drain induced barrier lowering, kink effect, floating body effect, and subthreshold leakage. The model has been applied to MOSFETs, SOI transistors, GaAs MESFETs, GaAs based HEMTs, amorphous, polysilicon and organic TFTs, AlGaN/GaN HEMTs, and to new emerging hetero-dimensional transistors. For compound semiconductor devices, additional effects, such as frequency dispersion and temperature dependence of model parameters, and gate leakage current, including hot-carrier leakage, have been accounted for.
Index Terms:
field effect transistors, device modeling, parameter extraction, SPICE
Citation:
Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal, "Transistor Modeling for the VDSM Era," isqed, pp.37, First International Symposium on Quality of Electronic Design, 2000
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