Over the last 10 years, Integrated circuits complexity has blossomed to the point where system time to market is critically dependant on IC "correctness" as intended by the "designer". In many cases, the "designer" is a team of engineers - not an individual, and the "tools" are a flow - not a series of point tools. To a first approximation, the industry wafer fabrication process has achieved a level of "correctness", or "quality" that exceeds that of the EDA tools being used to create and implement the IC design. Integrated EDA tools lag behind Moore's law, and are the primary cause of the "non-correctness" being experienced with many complex IC designs today. The EDA industry needs to unify behind new "high quality design flow" criteria that the user community believes in and can integrate into established system design environments. One of the critical issues facing the design community is how to select a high quality EDA design tool flow in this environment, and what should EDA tool providers do to close the gap with Moore's Law?