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1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97)
Toward more advanced usage of instruction level parallelism by a very large data path processor architecture
Taipei, Taiwan
December 18-December 20
ISBN: 0-8186-8259-0
ASCII Text
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H. Tanaka, "Toward more advanced usage of instruction level parallelism by a very large data path processor architecture," Parallel Architectures, Algorithms, and Networks, International Symposium on, pp. 437, 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 1997.
 
 
BibTex
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@article{ 10.1109/ISPAN.1997.645134,
author = {H. Tanaka},
title = {Toward more advanced usage of instruction level parallelism by a very large data path processor architecture},
journal ={Parallel Architectures, Algorithms, and Networks, International Symposium on},
volume = {0},
year = {1997},
issn = {1087-4089},
pages = {437},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISPAN.1997.645134},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Architectures, Algorithms, and Networks, International Symposium on
TI - Toward more advanced usage of instruction level parallelism by a very large data path processor architecture
SN - 1087-4089
SP
EP
A1 - H. Tanaka,
PY - 1997
KW - parallel architectures; instruction level parallelism; very large data path processor; processor architecture; performance gain; microprocessor; instruction analysis; parallel gain
VL - 0
JA - Parallel Architectures, Algorithms, and Networks, International Symposium on
ER -
 
H. Tanaka, Dept. of Electr. Eng., Tokyo Univ., Japan
The architectural performance gain of a microprocessor is going to saturate because of the small gain of instruction level parallelism. In this paper, we discuss the design points and some tentative solutions to overcome this bottleneck and propose a processor architecture called Very Large Data Path. This architecture broadens the window of instruction analysis to extract 10 times of parallel gain compared with the conventional superscaler processors. This paper discusses the system elements and shows some preliminary evaluation results.
Index Terms:
parallel architectures; instruction level parallelism; very large data path processor; processor architecture; performance gain; microprocessor; instruction analysis; parallel gain
Citation:
H. Tanaka, "Toward more advanced usage of instruction level parallelism by a very large data path processor architecture," ispan, pp.437, 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 1997
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