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1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97)
An efficient class of SEC-DED-AUED codes
Taipei, Taiwan
December 18-December 20
ISBN: 0-8186-8259-0
D.K. Bhattacharryya, Dept. of Comput. Sci., Tezpur Univ., Assam, India
S. Nandi, Dept. of Comput. Sci., Tezpur Univ., Assam, India
In this paper, an efficient method for constructing a class of Single Error Correcting and Double Error Detecting and All Unidirectional Error Detecting (SEC-DED-AUED) codes has been presented. The encoding/decoding algorithms proposed with this method can be implemented with a simple and faster hardware. Also, in ROM based implementation, it results in significant saving of word-length. This scheme in general, needs less or equal number of check bits.
Index Terms:
error correction codes; SEC-DED-AUED codes; codes; error correcting codes; error detecting codes; encoding; decoding
Citation:
D.K. Bhattacharryya, S. Nandi, "An efficient class of SEC-DED-AUED codes," ispan, pp.410, 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 1997
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