Massively parallel computers have been used for high performance computation in advanced science and technology. The Hypercube (HC) network has attractive properties such as strong connectivity, recursive interconnection, simple routing, and a good link complexity. However, as the number of processing elements (PEs) increases, the diameter and average distance of HC become large in proportion to a logarithm of the number of PEs. This causes a large latency in communication between PEs and consequently, it reduces system performance. To solve this problem, two approaches have been investigated. The first approach is a theoretical approach to find a network topology reducing a diameter and an average distance between PEs. The second approach reduces the physical distances between PEs by integrating a large interconnection on a small chip for a silicon wafer. In this paper, we propose a new interconnection network ; The HCQ (Horizontal Rotate Crossed Cube) by taking into account a WSI implementation. Theoretical network properties such as the diameter, the average distance, a routing algorithm are discussed in detail. It is shown that HCQ is a suitable network topology for massively parallel computers for WSI.