By gathering multiple processors in one LSI chip, communication delay between processors becomes shortening and then efficient fine/medium grain parallel processing can be realized. The authors propose new processor architecture called "OCMP (On-Chip Multi-Processing Architecture)". OCMP has two characteristics; one is the instruction level dispatching mechanism, and the other is the divided cache system. OCMP employs fork-join type parallel processing model in order to simplify the dispatching mechanism. By dividing cache system into shared cache and private one, the cache coherence problem between processors in a same chip is removed and access conflict on shared cache is also relaxed. OCMP is evaluated with the instruction level simulator which developed by the authors. Two type of instruction level dispatching mechanisms are compared with each other. Memory access mechanism is evaluated with various parameters such as memory access cost, the degree of simultaneous access to shared cache, and so on.