1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97)
A Scalable Cache Coherent Architecture for Large-Scale Mesh-Connected Multiprocessors
Taipei, Taiwan
December 18-December 20
ISBN: 0-8186-8259-0
Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data, however, most protocols suffer from extraneous cache invalidates or updates due to insufficient pointers. We focus on large-scale mesh-connected multiprocessors built on top of wormhole and dimension ordered routing networks. In such networks, worms are major bricks for communications, which transit all the intermediate nodes on its way to a destination. From such an observation, we propose a new directory-based protocol "DirQ" with limited pointers, which can represent either one node or a set of nodes when being widely shared. For sqrt{N} x sqrt{N} processors system, our protocol needs \Theta(N^{3/2}\log{N}) bits for directory memory which is much more scalable compared to the full-map protocol. In terms of latency and traffic volume for cache coherence, our analytic models show that "Dir Q" outperforms other limited protocols, and further comparable to the full-map one.
Index Terms:
mesh-interconnect, multiprocessor, cache coherence, directory-based protocol, wormhole routing, dimension ordered routing
Citation:
Yunseok Rhee, Joonwon Lee, "A Scalable Cache Coherent Architecture for Large-Scale Mesh-Connected Multiprocessors," ispan, pp.64, 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 1997