1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96)
Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors
Beijing, CHINA
June 12-June 14
ISBN: 0-8186-7460-1
I. Ahmad, Dept. of Comput. Sci., Hong Kong Univ., Hong Kong
Min-You Wu, Dept. of Comput. Sci., Hong Kong Univ., Hong Kong
In this paper, we survey algorithms that allocate a parallel program represented by an edge-weighted directed acyclic graph (DAG), also called a task graph or macro-dataflow graph, to a set of homogeneous processors, with the objective of minimizing the completion time. We analyze 21 such algorithms and classify them into four groups. The first group includes algorithms that schedule the DAG to a bounded number of processors directly. These algorithms are called the bounded number of processors (BNP) scheduling algorithms. The algorithms in the second group schedule the DAG to an unbounded number of clusters and are called the unbounded number of clusters (UNC) scheduling algorithms. The algorithms in the third group schedule the DAG using task duplication and are called the task duplication based (TDB) scheduling algorithms. The algorithms in the fourth group perform allocation and mapping on arbitrary processor network topologies. These algorithms are called the arbitrary processor network (APN) scheduling algorithms. The design philosophies and principles behind these algorithms are discussed, and the performance of all of the algorithms is evaluated and compared against each other on a unified basis by using various scheduling parameters.
Index Terms:
scheduling; processor scheduling; parallel programming; data flow graphs; task graphs; parallel processors; edge-weighted directed acyclic graph; dataflow graph; scheduling; bounded number of processors scheduling; arbitrary processor network
Citation:
I. Ahmad, Yu-Kwong Kwok, Min-You Wu, "Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors," ispan, pp.207, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996