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1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96)
Event Ordering Condition for Correct Executions in Shared-Memory Systems
Beijing, CHINA
June 12-June 14
ISBN: 0-8186-7460-1
ASCII Text
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Weiwu Hu, Peisu Xia, "Event Ordering Condition for Correct Executions in Shared-Memory Systems," Parallel Architectures, Algorithms, and Networks, International Symposium on, pp. 84, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996.
 
 
BibTex
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@article{ 10.1109/ISPAN.1996.508965,
author = {Weiwu Hu and Peisu Xia},
title = {Event Ordering Condition for Correct Executions in Shared-Memory Systems},
journal ={Parallel Architectures, Algorithms, and Networks, International Symposium on},
volume = {0},
year = {1996},
issn = {1087-4089},
pages = {84},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISPAN.1996.508965},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Architectures, Algorithms, and Networks, International Symposium on
TI - Event Ordering Condition for Correct Executions in Shared-Memory Systems
SN - 1087-4089
SP
EP
A1 - Weiwu Hu,
A1 - Peisu Xia,
PY - 1996
KW - shared-memory multiprocessor
KW - sequential consistency
KW - event ordering
KW - write atomic write nonatomic
KW - correct execution
VL - 0
JA - Parallel Architectures, Algorithms, and Networks, International Symposium on
ER -
 
Weiwu Hu, Center of High Performance Computing Institute of Computing Technology Academia Sinica
Peisu Xia, Center of High Performance Computing Institute of Computing Technology Academia Sinica
In this paper, event order for correct executions in shared-memory systems is systematically investigated with the help of set theory. Starting from a proposed program model which abstracts the memory access characteristics of parallel programs, executions of sequential memory accesses, atomic memory accesses, and nonatomic memory accesses are studied. The necessary and sufficient condition for correct executions in write atomic and write nonatomic systems are presented and proved.
Index Terms:
shared-memory multiprocessor, sequential consistency, event ordering, write atomic write nonatomic, correct execution
Citation:
Weiwu Hu, Peisu Xia, "Event Ordering Condition for Correct Executions in Shared-Memory Systems," ispan, pp.84, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996
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