loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96)
The Multiplus/Mulplix Parallel Processing Environment
Beijing, CHINA
June 12-June 14
ISBN: 0-8186-7460-1
ASCII Text
x 
 
J.S. Aude, A.M. Meslin, C.M.P. Santos, G. Bronstein, L.F.M. Cordeiro, M.O. Barros, M. Joao, Jr., S.C. Oliveira, "The Multiplus/Mulplix Parallel Processing Environment," Parallel Architectures, Algorithms, and Networks, International Symposium on, pp. 50, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996.
 
 
BibTex
x
 
@article{ 10.1109/ISPAN.1996.508960,
author = {J.S. Aude and A.M. Meslin and C.M.P. Santos and G. Bronstein and L.F.M. Cordeiro and M.O. Barros and M. Joao, Jr. and S.C. Oliveira},
title = {The Multiplus/Mulplix Parallel Processing Environment},
journal ={Parallel Architectures, Algorithms, and Networks, International Symposium on},
volume = {0},
year = {1996},
issn = {1087-4089},
pages = {50},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISPAN.1996.508960},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Architectures, Algorithms, and Networks, International Symposium on
TI - The Multiplus/Mulplix Parallel Processing Environment
SN - 1087-4089
SP
EP
A1 - J.S. Aude,
A1 - A.M. Meslin,
A1 - C.M.P. Santos,
A1 - G. Bronstein,
A1 - L.F.M. Cordeiro,
A1 - M.O. Barros,
A1 - M. Joao, Jr.,
A1 - S.C. Oliveira,
PY - 1996
KW - Distributed Shared-Memory Architectures
KW - Multistage Interconnection Network
KW - Cache Consistency
KW - Threads
KW - Synchronization
KW - Parallel Programming Environments
VL - 0
JA - Parallel Architectures, Algorithms, and Networks, International Symposium on
ER -
 
J.S. Aude, NCE/UFRJ, Federal University of Rio de Janeiro
A.M. Meslin, NCE/UFRJ, Federal University of Rio de Janeiro
C.M.P. Santos, NCE/UFRJ, Federal University of Rio de Janeiro
G. Bronstein, NCE/UFRJ, Federal University of Rio de Janeiro
L.F.M. Cordeiro, NCE/UFRJ, Federal University of Rio de Janeiro
M.O. Barros, NCE/UFRJ, Federal University of Rio de Janeiro
M. Joao, Jr., NCE/UFRJ, Federal University of Rio de Janeiro
S.C. Oliveira, NCE/UFRJ, Federal University of Rio de Janeiro
The MULTIPLUS project aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming environment for the MULTIPLUS architecture by providing facilities for the creation of threads, the allocation of private and shared memory space and the efficient use of synchronization primitives. After presenting the main features of the MULTIPLUS architecture and of the MULPLIX operating system, the paper describes in detail the design and the implementation of the three MULTIPLUS architecture basic hardware modules: the Processing Element, the Multistage Interconnection Network and the I/O Processor. In addition, the definition of the MULPLIX parallel programming primitives is discussed and their use is illustrated through an example. Finally, future directions in the development of the MULTIPLUS research project are commented.
Index Terms:
Distributed Shared-Memory Architectures, Multistage Interconnection Network, Cache Consistency, Threads, Synchronization, Parallel Programming Environments
Citation:
J.S. Aude, A.M. Meslin, C.M.P. Santos, G. Bronstein, L.F.M. Cordeiro, M.O. Barros, M. Joao, Jr., S.C. Oliveira, "The Multiplus/Mulplix Parallel Processing Environment," ispan, pp.50, 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), 1996
Usage of this product signifies your acceptance of the Terms of Use.