In logic simulation, we often need to evaluate two-valued logic functions in the presence of unknown inputs. However, a naive method often produces imprecise results. In these cases, we can obtain precise values by evaluating the regular ternary logic function for the given two-valued logic function. This paper shows a hardware realization of regular ternary logic functions. We use look-up table (LUT) cascades to implement double-rail logic representation. The evaluation time for n-input logic function is O(n) They require much smaller amount of hardware than naive memory implementations.