A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions

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34th International Symposium on Multiple-Valued Logic (ISMVL'04)

University of Toronto, Toronto, Canada

May 19-May 22

ISBN: 0-7695-2130-4

	ASCII Text	x
	Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, "A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions," Multiple-Valued Logic, IEEE International Symposium on, pp. 269-274, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004.

	BibTex	x
	@article{ 10.1109/ISMVL.2004.1319953, author = {Hiroshi Inokawa and Yasuo Takahashi and Katsuhiko Degawa and Takafumi Aoki and Tatsuo Higuchi}, title = {A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2004}, issn = {0195-623X}, pages = {269-274}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319953}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions SN - 0195-623X SP269 EP274 A1 - Hiroshi Inokawa, A1 - Yasuo Takahashi, A1 - Katsuhiko Degawa, A1 - Takafumi Aoki, A1 - Tatsuo Higuchi, PY - 2004 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Hiroshi Inokawa, NTT Corporation

Yasuo Takahashi, NTT Corporation

Katsuhiko Degawa, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319953

Guidelines for designing multi-input multi-output counters based on single-electron transistor (SET) logic gate family are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifting. Circuit simulation using a physics-based SET model reveals that the counter operates at a moderately high speed and with ultra-low power consumption.

Citation:

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, "A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions," ismvl, pp.269-274, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004

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