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34th International Symposium on Multiple-Valued Logic (ISMVL'04)
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit
University of Toronto, Toronto, Canada
May 19-May 22
ISBN: 0-7695-2130-4
ASCII Text
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Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim, "Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit," Multiple-Valued Logic, IEEE International Symposium on, pp. 198-203, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004.
 
 
BibTex
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@article{ 10.1109/ISMVL.2004.1319941,
author = {Soo Jin Park and Byoung Hee Yoon and Kwang Sub Yoon and Heung Soo Kim},
title = {Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2004},
issn = {0195-623X},
pages = {198-203},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319941},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit
SN - 0195-623X
SP198
EP203
A1 - Soo Jin Park,
A1 - Byoung Hee Yoon,
A1 - Kwang Sub Yoon,
A1 - Heung Soo Kim,
PY - 2004
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Soo Jin Park, INHA University
Byoung Hee Yoon, INHA University
Kwang Sub Yoon, INHA University
Heung Soo Kim, INHA University
A multi-valued Logic (MVL) pass gate is an important element to configure multi-valued logic. Multiple logical levels which are different from binary pass gates are required to be discriminated in MVL pass gates [1]. In this paper, we designed the Quaternary MIN (QMIN)/negated MIN (QMIN) gate, the Quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gate. And also we designed Quaternary Truncated Difference (QTD) gate using vMOS down literal circuit (DLC). DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed by vMOS DLC. The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltages and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.
Citation:
Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim, "Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit," ismvl, pp.198-203, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004
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