This paper presents a new common-bus architecture for high-speed data transfer with transferring vast quantities of data between modules inside a VLSI chip. In the intrachip data transfer, start addresses of the source and destination modules and the number of data are sent to the target modules at the .rst step, which is called "address presetting". After that, only the data are transferred with the maximum width of the bus, which results in achieving high throughput of bus communication. Moreover, the use of multiple-valued data encoding together with a multiple-valued current-mode circuit technique for multi-level signal detectors makes it possible to perform higher throughput of data transfer under the bus-width constraint. In case of a 64-line bus, it is demonstrated that the peak throughput using the proposed architecture is 8 times higher than that using a binary bus architecture based on direct memory access control. Its power dissipation is reduced to about 20 percent in comparison with that of the direct memory access one under the normalized throughput in a 0.18µm CMOS process.