A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC

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	Similar Articles Articles by Omid Mirmotahari Articles by Yngvar Berg

34th International Symposium on Multiple-Valued Logic (ISMVL'04)

University of Toronto, Toronto, Canada

May 19-May 22

ISBN: 0-7695-2130-4

	ASCII Text	x
	Omid Mirmotahari, Yngvar Berg, "A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC," Multiple-Valued Logic, IEEE International Symposium on, pp. 135-138, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004.

	BibTex	x
	@article{ 10.1109/ISMVL.2004.1319932, author = {Omid Mirmotahari and Yngvar Berg}, title = {A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2004}, issn = {0195-623X}, pages = {135-138}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319932}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC SN - 0195-623X SP135 EP138 A1 - Omid Mirmotahari, A1 - Yngvar Berg, PY - 2004 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Omid Mirmotahari, University of Oslo

Yngvar Berg, University of Oslo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319932

In this paper we present several different proposals for implementing a multiple-valued (MV) semi-floating-gate (SFG) D-latch. This paper aims to illustrate the advantages and disadvantages of each approach. Measurements from a fabricated chip at a 0.6?m CUP process is included for verifying the detailed arguments.

Citation:

Omid Mirmotahari, Yngvar Berg, "A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC," ismvl, pp.135-138, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004

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