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Fifth IEEE Symposium on Computers and Communications (ISCC 2000)
Design and Implementation of an ABR Server in a Shared-Bus ATM Switch
Antibes, France
July 04-July 06
ISBN: 0-7695-0722-0
ASCII Text
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E. Zervanos, G. Stassinopoulos, "Design and Implementation of an ABR Server in a Shared-Bus ATM Switch," Computers and Communications, IEEE Symposium on, pp. 366, Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 2000.
 
 
BibTex
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@article{ 10.1109/ISCC.2000.860665,
author = {E. Zervanos and G. Stassinopoulos},
title = {Design and Implementation of an ABR Server in a Shared-Bus ATM Switch},
journal ={Computers and Communications, IEEE Symposium on},
volume = {0},
year = {2000},
issn = {1530-1346},
pages = {366},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISCC.2000.860665},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Computers and Communications, IEEE Symposium on
TI - Design and Implementation of an ABR Server in a Shared-Bus ATM Switch
SN - 1530-1346
SP
EP
A1 - E. Zervanos,
A1 - G. Stassinopoulos,
PY - 2000
KW - Networks
KW - ATM
KW - ABR
KW - Switching
VL - 0
JA - Computers and Communications, IEEE Symposium on
ER -
 
E. Zervanos, National Technical University of Athens
G. Stassinopoulos, National Technical University of Athens
This paper concerns the design and development of an Available Bit Rate (ABR) server as part of an Asynchronous Transfer Mode (ATM) switch. The overall implementation is based on a shared medium switching architecture, a Time Division Multiplexed (TDM) bus, providing both modularity and high reliability. The paper focalizes on hardware architecture of the entire system and presents its basic software architecture.
Index Terms:
Networks, ATM, ABR, Switching
Citation:
E. Zervanos, G. Stassinopoulos, "Design and Implementation of an ABR Server in a Shared-Bus ATM Switch," iscc, pp.366, Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 2000
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