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12th. International Parallel Processing Symposium
ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration
Orlando, Florida
March 30-April 03
ISBN: 0-8186-8403-8
ASCII Text
x 
 
D. Davis, J. Harris, "ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration," Parallel Processing Symposium, International, pp. 0616, 12th. International Parallel Processing Symposium, 1998.
 
 
BibTex
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@article{ 10.1109/IPPS.1998.669990,
author = {D. Davis and J. Harris},
title = {ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration},
journal ={Parallel Processing Symposium, International},
volume = {0},
year = {1998},
isbn = {0-8186-8403-8},
pages = {0616},
doi = {http://doi.ieeecomputersociety.org/10.1109/IPPS.1998.669990},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Processing Symposium, International
TI - ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration
SN - 0-8186-8403-8
SP
EP
A1 - D. Davis,
A1 - J. Harris,
PY - 1998
VL - 0
JA - Parallel Processing Symposium, International
ER -
 
Citation:
D. Davis, J. Harris, "ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration," ipps, pp.0616, 12th. International Parallel Processing Symposium, 1998
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