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18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3 Santa Fe, New Mexico April 26-April 30 ISBN: 0-7695-2132-0 Table of Contents
Of Gates and Wires (Abstract)
Patrick Lysaght, Xilinx Research Labs
Delon Levi, Xilinx Research Labs pp. 132a
E. J. Swankoski, Applied Research Laboratory
V. Narayanan, Pennsylvania State University
M. Kandemir, Pennsylvania State University
M. J. Irwin, Pennsylvania State University pp. 132b
Ashutosh S. Dhodapkar, University of Wisconsin-Madison
James E. Smith, University of Wisconsin-Madison pp. 133a
S. Sezer, Queen?s University Belfast
C. Toal, Queen?s University Belfast
E. Garcia, Queen?s University Belfast
V. Stewart, Queen?s University Belfast pp. 133b
Ali Ahmadinia, University of Erlangen-Nuremberg
Christophe Bobda, University of Erlangen-Nuremberg
Marcus Bednara, University of Erlangen-Nuremberg
Jürgen Teich, University of Erlangen-Nuremberg pp. 134a
Emanuele Lattanzi, University of Urbino
Aman Gayasen, Penn State University
Mahmuth Kandemir, Penn State University
Vijaykrishnan Narayanan, Penn State University
Luca Benini, University of Bologna
Alessandro Bogliolo, University of Urbino pp. 134b
Michael Ullmann, Universit?t Karlsruhe
Michael H?, Universit?t Karlsruhe
Bj? Grimm, Universit?t Karlsruhe
J? Becker, Universit?t Karlsruhe pp. 135a
Sebastian Lange, University of Leipzig
Martin Middendorf, University of Leipzig pp. 135b
Stefan Ihmor, University of Paderborn
Wolfram Hardt, Chemnitz University of Technology pp. 136a
Esam El-Araby, The George Washington University
Mohamed Taher, The George Washington University
Kris Gaj, George Mason University
Tarek El-Ghazawi, The George Washington University
David Caliga, SRC Computers
Nikitas Alexandridis, The George Washington University pp. 136b
Patrick Schaumont, University of California at Los Angeles
Kazuo Sakiyama, University of California at Los Angeles
Alireza Hodjat, University of California at Los Angeles
Ingrid Verbauwhede, University of California at Los Angeles pp. 137
V. Kalenteridis, Aristotle University of Thessaloniki
H. Pournara, Aristotle University of Thessaloniki
K. Siozios, Democritus University of Thrace
K. Tatas, Democritus University of Thrace
G. Koytroympezis, Democritus University of Thrace
I. Pappas, Aristotle University of Thessaloniki
S. Nikolaidis, Aristotle University of Thessaloniki
S. Siskos, Aristotle University of Thessaloniki
D. J. Soudris, Democritus University of Thrace
A. Thanailakis, Democritus University of Thrace pp. 138a
Michael Huebner, Universitaet Karlsruhe
Michael Ullmann, Universitaet Karlsruhe
Florian Weissel, Universitaet Karlsruhe
Juergen Becker, Universitaet Karlsruhe pp. 138b
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs (Abstract)
Renqiu Huang, University of Cincinnati
Ranga Vemuri, University of Cincinnati pp. 139a
Doris Ching, University of California at Los Angeles
Patrick Schaumont, University of California at Los Angeles
Ingrid Verbauwhede, University of California at Los Angeles pp. 139b
Klaus Danne, University of Paderborn
Christophe Bobda, University of Erlangen-Nuremberg pp. 140a
Manish Handa, University of Cincinnati
Ranga Vemuri, University of Cincinnati pp. 140b
H. Kalte, University of Paderborn
M. Porrmann, University of Paderborn
U. R?ckert, University of Paderborn pp. 141a
Cristinel Ababei, University of Minnesota
Kia Bazargan, University of Minnesota pp. 141b
Tyson S. Hall, Georgia Institute of Technology
Christopher M. Twigg, Georgia Institute of Technology
Paul Hasler, Georgia Institute of Technology
David V. Anderson, Georgia Institute of Technology pp. 142b pp. 143a
Adronis Niyonkuru, Universität der Bundeswehr Hamburg
Hans Christoph Zeidler, Universität der Bundeswehr Hamburg pp. 143b
A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2^m) (Abstract)
Nazar A. Saqib, Instituto Politécnico Nacional
Francisco Rodríguez-Henriquez, Instituto Politécnico Nacional
Arturo Díaz-Pérez, Instituto Politécnico Nacional pp. 144a
Shigeyuki Takano, University of Aizu pp. 144b
Jing Huang, Northeastern University
Mehdi B. Tahoori, Northeastern University
Fabrizio Lombardi, Northeastern University pp. 145a
Maya Gokhale, Los Alamos National Laboratory
Paul Graham, Los Alamos National Laboratory
Eric Johnson, Brigham Young University
Nathan Rollins, Brigham Young University
Michael Wirthlin, Brigham Young University pp. 145b
Lilian Bossuet, Universit? de Bretagne Sud
Guy Gogniat, Universit? de Bretagne Sud
Wayne Burleson, University of Massachusetts at Amherst pp. 146a
RECASTER: Synthesis of Fault-Tolerant Embedded Systems Based on Dynamically Reconfigurable FPGAs (Abstract)
Alice M. Tokarnia, University of Campinas pp. 146b
Klaus Waldschmidt, J. W. Goethe University pp. 147a
Paul M. Heysters, University of Twente
Gerard K. Rauwerda, University of Twente
Gerard J. M. Smit, University of Twente pp. 147b
Frank Hannig, University of Erlangen-Nuremberg
Hritam Dutta, University of Erlangen-Nuremberg
Jürgen Teich, University of Erlangen-Nuremberg pp. 148a
Yosi Ben-Asher, Haifa University
Daniel Citron, IBM Haifa Research Lab
Gadi Haber, IBM Haifa Research Lab pp. 148b
Gokul Govindu, University of Southeren California
Seonil Choi, University of Southeren California
Viktor Prasanna, University of Southeren California
Vikash Daga, Satyam Computer Services Ltd.
Sridhar Gangadharpalli, Satyam Computer Services Ltd.
V. Sridhar, Satyam Computer Services Ltd. pp. 149a
Gokul Govindu, University of Southern California
Ling Zhuo, University of Southern California
Seonil Choi, University of Southern California
Viktor Prasanna, University of Southern California pp. 149b
Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications (Abstract)
Sami Khawam, University of Edinburgh
Tughrul Arslan, University of Edinburgh and Institute for System Level Integration
Fred Westall, EPSON Scotland Design Centre pp. 150a
Mitchell J. Myjak, Washington State University
Jos? G. Delgado-Frias, Washington State University pp. 150b
Al Strelzoff, Cadence Design Systems pp. 151a
Kazuyuki Maruo, Advantest Laboratories Ltd.
Masayoshi Ichikawa, Advantest Corporation
Naoto Miyamoto, Tohoku University
Leo Karnan, Tohoku University
Takahiro Yamaguchi, Advantest Laboratories Ltd.
Koji Kotani, Tohoku University
Tadahiro Ohmi, Tohoku University pp. 151b
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays (Abstract)
A. Manoj Kumar, Indian Institute of Technology Madras
B Jayaram, Indian Institute of Technology Madras
R. Manimegalai, Indian Institute of Technology Madras
V. Kamakoti, Indian Institute of Technology Madras pp. 152 Usage of this product signifies your acceptance of the Terms of Use.
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