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18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3
Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array
Santa Fe, New Mexico
April 26-April 30
ISBN: 0-7695-2132-0
Janusz A. Starzyk, Ohio University
Yongtao Guo, Ohio University
Zhineng Zhu, Ohio University
In this paper, we describe a new dynamically reconfigurable neuron hardware architecture based on the modified Xilinx Picoblaze microcontroller and self-organizing learning array (SOLAR) algorithm reported earlier. This architecture is aiming at using hundreds of traditional reconfigurable field programmable gate arrays (FPGAs) to build the SOLAR learning machine. SOLAR has many advantages over traditional neural network hardware implementation. Neurons are optimized for area and speed, and the whole system is dynamically self-reconfigurable during the runtime. The system architecture is expandable to a large multiple-chip system.
Citation:
Janusz A. Starzyk, Yongtao Guo, Zhineng Zhu, "Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array," ipdps, vol. 4, pp.143a, 18th International Parallel and Distributed Processing Symposium (IPDPS'04) - Workshop 3, 2004
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