This paper focuses on a mixed coarse-granular and fine-granular re-configurable architecture that is used to build hardware testbenches for the verification of ASICs or system-on-a-chip designs. Here, "coarse-granular" architecture refers to micro-sequencers, and "fine-granular" architecture refers to FPGAs. Hardware testbenches are derived from behavioral testbenches and testcases, which are written as micro-sequences. While the part of a testbench that controls the execution of the testcases is mapped to the coarse-granular architecture, the part that is responsible for the low-level protocol operations is mapped to the fine-granular architecture. The testcases are compiled into the program memories of the coarse-granular architecture. The mixed-granularity re-configurable architecture reduces modeling- and configuration-time as compared to a pure fine-granular solution. But it keeps the advantage of flexibility.