This paper presents an application-specific architecture for reconfigurable hardware that meets requirements of embedded configurability. Additionally, it allows for single cycle context switching at runtime. No specific FPGA technology is necessary, but the standard cell design flow and some enhancements are used to implement reconfigurability for the scope of pre-known applications. Several netlists are mapped on the same array of fixed basic cells. The interconnect effort and the number of configuration bits is minimized by inserting multiplexors whenever necessary. The presented architecture allows for significant area reduction of 30% and more when comparing it to the traditional approach of parallel implemented standard cell macros.