International Parallel and Distributed Processing Symposium (IPDPS'03)
Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design
Nice, France
April 22-April 26
ISBN: 0-7695-1926-1
We present an automated temporal partitioning applied on the data-path part of an algorithm for the reconfigurable embedded system design. The originality of this partitioning is that it minimize the number of cells needed to implement the data-path of an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resources needed. This optimizing approach can be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.
Citation:
C. Tanougast, Y. Berviller, P. Brunet, S. Weber, "Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design," ipdps, pp.178a, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003