More and more reconfigurable architectures are today available as IP cores for SoC designers. These ones often differ according to several parameters (granularity, reconfiguration mode, topology…). Therefore, it is not straightforward to compare different architectures and choose the right one considering a given set of requirements. This paper proposes a general model for reconfigurable architectures and gives a set of metrics which prove useful for architecture characterization. These metrics are detailed and their interests is shown on several digital signal processing architectures. The methodology is then illustrated on a parametrable dynamically reconfigurable architecture: The Systolic Ring.