Real-Time Primer Design for DNA Chips

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by H. Simmler Articles by H. Singpiel Articles by R. Männer

International Parallel and Distributed Processing Symposium (IPDPS'03)

Nice, France

April 22-April 26

ISBN: 0-7695-1926-1

	ASCII Text	x
	H. Simmler, H. Singpiel, R. Männer, "Real-Time Primer Design for DNA Chips," Parallel and Distributed Processing Symposium, International, pp. 153b, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003.

	BibTex	x
	@article{ 10.1109/IPDPS.2003.1213288, author = {H. Simmler and H. Singpiel and R. Männer}, title = {Real-Time Primer Design for DNA Chips}, journal ={Parallel and Distributed Processing Symposium, International}, volume = {0}, year = {2003}, issn = {1530-2075}, pages = {153b}, doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2003.1213288}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Processing Symposium, International TI - Real-Time Primer Design for DNA Chips SN - 1530-2075 SP EP A1 - H. Simmler, A1 - H. Singpiel, A1 - R. Männer, PY - 2003 KW - Primer design KW - HPC KW - High performance parallel architecture KW - Hardware accelerator KW - FPGA VL - 0 JA - Parallel and Distributed Processing Symposium, International ER -

H. Simmler, Acconovis GmbH

H. Singpiel, Acconovis GmbH

R. Männer, Universit?t Mannheim

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2003.1213288

The design of PCR or DNA Chip experiments is a time consuming process where bioinformatics is extensively used. Selecting primers for the DNA chip requires a complex algorithm. Based on several parameters an optimized set of primers is computed for a given gene sequence. This paper describes a parallel architecture that performs the primer selection on a hardware accelerator. This parallel architecture reduces the complexity of the time extensive part from O(n²+m²+mn) to O(1). Compared to software, the parallel architecture gains a speedup of factor 500 using a PCI hardware accelerator. This enables to compute the primers in real-time.

Index Terms:

Primer design, HPC, High performance parallel architecture, Hardware accelerator, FPGA

Citation:

H. Simmler, H. Singpiel, R. Männer, "Real-Time Primer Design for DNA Chips," ipdps, pp.153b, International Parallel and Distributed Processing Symposium (IPDPS'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.