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Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
A Scan-Bist Environment for Testing Embedded Memories
Isle of Bendor, France
July 08-July 10
ISBN: 0-7695-1641-6
ASCII Text
x 
 
F. Karimi, F. Lombardi, "A Scan-Bist Environment for Testing Embedded Memories," On-Line Testing Workshop, IEEE International, pp. 211, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002.
 
 
BibTex
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@article{ 10.1109/OLT.2002.1030221,
author = {F. Karimi and F. Lombardi},
title = {A Scan-Bist Environment for Testing Embedded Memories},
journal ={On-Line Testing Workshop, IEEE International},
volume = {0},
year = {2002},
isbn = {0-7695-1641-6},
pages = {211},
doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030221},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - On-Line Testing Workshop, IEEE International
TI - A Scan-Bist Environment for Testing Embedded Memories
SN - 0-7695-1641-6
SP
EP
A1 - F. Karimi,
A1 - F. Lombardi,
PY - 2002
KW - null
VL - 0
JA - On-Line Testing Workshop, IEEE International
ER -
 
F. Karimi, LTX Corporation
F. Lombardi, Northeastern University
This paper presents a new IEEE 1149.1 compatible architecture as an intermediate environment for testing embedded memories. A BIST structure and a boundary scan are used for testing various memory configurations for programmability as well as improved controllability and observability. Its novelty is that features such as modularity, scalability with word size and adaptability to different memory configurations and testing requirements, are accomplished at relative ease. In the boundary scan, user-defined test modes are utilized so that basic modications to the elements of a seed algorithm can be generated very efficiently.
Citation:
F. Karimi, F. Lombardi, "A Scan-Bist Environment for Testing Embedded Memories," ioltw, pp.211, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002
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