This paper proposes a suitable on-line testing technique during the synthesis of complex electronic structures. On-line testability is addressed by exploiting time redundancy in the scheduled data flow graph. On-line testability constraints are taken into account at the scheduling and allocation tasks. The technique implements non-concurrent; semi-concurrent or fully concurrent on-line tests according to the ability of the synthesized structure.
Citation:
M. A. Naal, M. Rakotoar, E. Simeu, C. Aktouf, "Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach," ioltw, pp.184, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002