The recovery technique introduced in this paper can be implemented in new designs and may allow sequential circuits to recover from many temporary faults. It is assumed that errors will be detected by other means. The memory elements of the mission circuit are implemented with standard, slightly enhanced, scan-cells that work as stand-alone, needing no external control or support.
Index Terms:
Dependability, DFT, Sequential logic, BST
Citation:
Jose Miguel Vieira dos Santos, "Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells," ioltw, pp.179, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002