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Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Analysis of SEU Effects in a Pipelined Processor
Isle of Bendor, France
July 08-July 10
ISBN: 0-7695-1641-6
ASCII Text
x 
 
M. Rebaudengo, M. Sonza Reorda, M. Violante, "Analysis of SEU Effects in a Pipelined Processor," On-Line Testing Workshop, IEEE International, pp. 112, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002.
 
 
BibTex
x
 
@article{ 10.1109/OLT.2002.1030193,
author = {M. Rebaudengo and M. Sonza Reorda and M. Violante},
title = {Analysis of SEU Effects in a Pipelined Processor},
journal ={On-Line Testing Workshop, IEEE International},
volume = {0},
year = {2002},
isbn = {0-7695-1641-6},
pages = {112},
doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030193},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - On-Line Testing Workshop, IEEE International
TI - Analysis of SEU Effects in a Pipelined Processor
SN - 0-7695-1641-6
SP
EP
A1 - M. Rebaudengo,
A1 - M. Sonza Reorda,
A1 - M. Violante,
PY - 2002
KW - null
VL - 0
JA - On-Line Testing Workshop, IEEE International
ER -
 
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the effects of SEUs affecting pipelines and caches. In this paper we report an analysis of a commercial processor core where the effects of SEUs located in the processor pipeline and cache memories are studied. Moreover, the obtained results are compared with those software-based approaches provide. Experimental results show that software-based approaches may lead to errors during the failure rate estimation of up to 400%.
Citation:
M. Rebaudengo, M. Sonza Reorda, M. Violante, "Analysis of SEU Effects in a Pipelined Processor," ioltw, pp.112, Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002
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