This paper presents methods for designing totally self-checking Mealy Type synchronous sequential circuits (SSCs). We use implementations of the output and the next state functions that are monotonic in state variables. The monotony enables the SSc to react to permanent faults differently than it does to transient faults. If the fault is permanent, the SSC will produce a non-code output, which will be detected as error by the checker after a number of clock cycles. In the case of a transient fault, the SSC is able to survive and to return to normal operation after a number of clock cycles.

A novel universal architecture of self-checking SSCs enabling to overcome the above contradiction is proposed. This architecture can be adopted both for reduction of the fault latency of a permanent fault and for increasing the SSC survivability with respect to a transient fault. A method for SSC synthesis for the proposed architecture is presented. This method is oriented to FPGA implementation.