Schemes providing a synchronous sequential circuit (SSC) or combinational circuit (CC) survivability for unidirectional transient and intermittent faults are suggested. They are based on doubling self-checking circuits with using a self-testing checker for one of them and masking a fault manifestation with OR, AND and MX circuits. The schemes ensure a correct behavior when any scheme permissible fault occurs. We mean single stuck-at faults at gates poles and d flip-flops poles of the scheme. A method of cutting overhead during survivable self-checking SSC design is proposed. It is oriented to only transient faults.