Abstract: One of several approaches for designing highly-reliable systems relies on using error detecting codes (EDCs) and implementing digital circuits as self-checking. One class of EDCs that has been very often used to implement self-checking circuits are Berger codes. Although several self-testing checkers (STCs) for Berger codes have been proposed in the past, they mostly present area and delay results based on gate counts and gate levels and not on real implementations. In this work we consider real implementations and present and evaluate the area, delay and power characteristics of STCs for modified Berger codes that are based on: (a) parallel counters and (b) sorting networks. Preliminary results indicate that STCs based on parallel counters are smaller and consume less power than the STCs based on sorting networks.