On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity

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	Similar Articles Articles by M. Pflanz Articles by K. Walther Articles by H.T. Vierhaus

Seventh International On-Line Testing Workshop

Taormina, Italy

July 09-July 11

ISBN: 0-7695-1290-9

	ASCII Text	x
	M. Pflanz, K. Walther, H.T. Vierhaus, "On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity," On-Line Testing Workshop, IEEE International, pp. 0051, Seventh International On-Line Testing Workshop, 2001.

	BibTex	x
	@article{ 10.1109/OLT.2001.937818, author = {M. Pflanz and K. Walther and H.T. Vierhaus}, title = {On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2001}, isbn = {0-7695-1290-9}, pages = {0051}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937818}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity SN - 0-7695-1290-9 SP EP A1 - M. Pflanz, A1 - K. Walther, A1 - H.T. Vierhaus, PY - 2001 VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

M. Pflanz, BTU Cottbus

K. Walther, BTU Cottbus

H.T. Vierhaus, BTU Cottbus

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937818

Abstract: This paper presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the Cross-Parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors.

Citation:

M. Pflanz, K. Walther, H.T. Vierhaus, "On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity," ioltw, pp.0051, Seventh International On-Line Testing Workshop, 2001

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