A Family of Self-Repair SRAM Cores

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	Similar Articles Articles by A. Benso Articles by S. Chiusano Articles by G. Di Natale Articles by P. Prinetto Articles by Monica Lobetti Bodoni

6th IEEE International On-Line Testing Workshop (IOLTW)

Palma de Mallorca, Spain

July 03-July 05

ISBN: 0-7695-0646-1

	ASCII Text	x
	A. Benso, S. Chiusano, G. Di Natale, P. Prinetto, Monica Lobetti Bodoni, "A Family of Self-Repair SRAM Cores," On-Line Testing Workshop, IEEE International, pp. 214, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000.

	BibTex	x
	@article{ 10.1109/OLT.2000.856639, author = {A. Benso and S. Chiusano and G. Di Natale and P. Prinetto and Monica Lobetti Bodoni}, title = {A Family of Self-Repair SRAM Cores}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2000}, isbn = {0-7695-0646-1}, pages = {214}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2000.856639}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - A Family of Self-Repair SRAM Cores SN - 0-7695-0646-1 SP EP A1 - A. Benso, A1 - S. Chiusano, A1 - G. Di Natale, A1 - P. Prinetto, A1 - Monica Lobetti Bodoni, PY - 2000 KW - Memory Self-Repair KW - BISR KW - Memory BIST VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

A. Benso, Politecnico di Torino

S. Chiusano, Politecnico di Torino

G. Di Natale, Politecnico di Torino

P. Prinetto, Politecnico di Torino

Monica Lobetti Bodoni, Siemens Information and Communication Networks S.p.A.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2000.856639

In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed On-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed, ranging from an external test to an On-line concurrent BIST.

Index Terms:

Memory Self-Repair, BISR, Memory BIST

Citation:

A. Benso, S. Chiusano, G. Di Natale, P. Prinetto, Monica Lobetti Bodoni, "A Family of Self-Repair SRAM Cores," ioltw, pp.214, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000

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