The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off the shelve VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis.