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6th IEEE International On-Line Testing Workshop (IOLTW)
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL
Palma de Mallorca, Spain
July 03-July 05
ISBN: 0-7695-0646-1
Fabian Vargas, Catholic University - PUCRS
Alexandre Amory, Catholic University - PUCRS
Raoul Velazco, TIMA-INPG Laboratory
We present hereafter a new approach to estimate the reliability of complex circuits used in harmful environments like radiation. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities (particle accelerators). In our case, we estimate the expected tolerance of the complex circuit with respect to SEU during the VHDL specification step. By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool.
Citation:
Fabian Vargas, Alexandre Amory, Raoul Velazco, "Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL," ioltw, pp.67, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000
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