Self-Testing of FPGA Delay Faults in the System Environment

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6th IEEE International On-Line Testing Workshop (IOLTW)

Palma de Mallorca, Spain

July 03-July 05

ISBN: 0-7695-0646-1

	ASCII Text	x
	Andrzej Krasniewski, "Self-Testing of FPGA Delay Faults in the System Environment," On-Line Testing Workshop, IEEE International, pp. 40, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000.

	BibTex	x
	@article{ 10.1109/OLT.2000.856610, author = {Andrzej Krasniewski}, title = {Self-Testing of FPGA Delay Faults in the System Environment}, journal ={On-Line Testing Workshop, IEEE International}, volume = {0}, year = {2000}, isbn = {0-7695-0646-1}, pages = {40}, doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2000.856610}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Workshop, IEEE International TI - Self-Testing of FPGA Delay Faults in the System Environment SN - 0-7695-0646-1 SP EP A1 - Andrzej Krasniewski, PY - 2000 KW - FPGA KW - delay faults KW - BIST KW - random testing VL - 0 JA - On-Line Testing Workshop, IEEE International ER -

Andrzej Krasniewski, Warsaw University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/OLT.2000.856610

We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.

Index Terms:

FPGA, delay faults, BIST, random testing

Citation:

Andrzej Krasniewski, "Self-Testing of FPGA Delay Faults in the System Environment," ioltw, pp.40, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000

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