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6th IEEE International On-Line Testing Workshop (IOLTW)
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures
Palma de Mallorca, Spain
July 03-July 05
ISBN: 0-7695-0646-1
ASCII Text
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M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco, "Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures," On-Line Testing Workshop, IEEE International, pp. 17, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000.
 
 
BibTex
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@article{ 10.1109/OLT.2000.856606,
author = {M. Rebaudengo and M. Sonza Reorda and M. Violante and P. Cheynet and B. Nicolescu and R. Velazco},
title = {Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures},
journal ={On-Line Testing Workshop, IEEE International},
volume = {0},
year = {2000},
isbn = {0-7695-0646-1},
pages = {17},
doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2000.856606},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - On-Line Testing Workshop, IEEE International
TI - Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures
SN - 0-7695-0646-1
SP
EP
A1 - M. Rebaudengo,
A1 - M. Sonza Reorda,
A1 - M. Violante,
A1 - P. Cheynet,
A1 - B. Nicolescu,
A1 - R. Velazco,
PY - 2000
KW - Software Fault-Tolerance
KW - Fault Injection
VL - 0
JA - On-Line Testing Workshop, IEEE International
ER -
 
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
P. Cheynet, TIMA Laboratory
B. Nicolescu, TIMA Laboratory
R. Velazco, TIMA Laboratory
This paper deals with a method able to provide a mi-coprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations, which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent on the adopted platform.
Index Terms:
Software Fault-Tolerance, Fault Injection
Citation:
M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco, "Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures," ioltw, pp.17, 6th IEEE International On-Line Testing Workshop (IOLTW), 2000
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